The invention relates to telecommunications and more particularly to a switch system having first and second Switch Fabrics each including a switch core and distributed Switch Core Access Layer (SCAL) elements.
Switching technology has made considerable use of traditional crossbar switches, which support high rates (up to 100 Gigabits and even more). Crossbar switches however present a so-called  less than  less than head of line blocking greater than  greater than  drawback which seriously limits the efficiency of the switching process. Additionally, crossbar switches are not suitable for handling small data packets, such as those used in Asynchronous Transfer Mode (A.T.M.) networks.
New switching techniques are thus required for handling the small packets of data sometimes used for transporting data, voice or video over telecommunication networks. Shared buffer switches have proven to be a very interesting direction of research. Shared buffer switching techniques support high switching rates and effective handling of small packets of data. In shared buffer switching, a central buffer is used for storing messages received from the input ports of the switch before they are switched (rerouted) towards the appropriate output ports. Each output port of the switch is associated with an output queue which stores the succession of addresses corresponding to the location of the different messages loaded in the central buffer prior to their extraction and delivery to the associated output port. The queuing process is located at the output level of the switch, which eliminates the  less than  less than head of line blocking greater than  greater than  drawback and also facilitates multicasting possibilities. Shared buffer switches can be enhanced by means of speed expansion and port expansion mechanisms. Examples of such shared buffer techniques can be found in European applications no 97480057.5, 97480056.7, 97480065.8, 96480129.4, 96480120.3 assigned to IBM. Additional prior art documents relating to shared buffer switching techniques can be found in European applications no 97480100.3, no 97480098.9, no 97480101.1, no 97480099.7, no 98480007.8 and no 98480006.0.
The capabilities of shared buffer switches are obviously limited by the physical size of the shared buffer, which limits the number of cells which can be concurrently processed. Performance requirements and circuit complexity limits the size of the shared buffer that can be employed in a single electronic module.
Another problem is how to improve the availability of the switch, particularly when maintenance operations must be performed. It is highly desirable to be able to continue packet switching even when a maintenance operation is being performed on one part of the switching system, for example by replacing a card or performing a system upgrade.
The expansion in the size of telecommunication networks and in the number and type of transactions occurring on such networks tend to increase the need for introduction of fault tolerance mechanisms in a switching system. This is particularly true when the switching system is part of a satellite or other critical application. In these applications, it is essential that the packet routing process continue, even if at a reduced performance level, when a part of the switching system fails. Fault tolerance mechanisms are generally expensive since the number of required electronic modules is generally doubled. Some of the added cost of the duplicate modules may be justifiable if the duplicate components are utilized during normal switch operation and not just when a partial switch failure has occurred.
An object of the present invention is to provide a buffer expansion architecture which supports efficient combination of the buffering possibilities of first and a second individual switching modules.
Another object of the present invention is to provide a switch based on an architecture which supports continued operations even when a maintenance operation is being performed on one part of the switch.
It is another object of the present invention to provide a fault tolerant switch based on a first and a second switching structure which advantageously uses the resources of both structures in the normal operations, and which can still be used, with possibly reduced performance when one of the structures is out of service.
It is a further object of the present invention to provide a switch having two switching fabrics which may be continuously checked and which uses very simple port adapters designed to operate at the normal rate.
A switch according to the invention includes first and second switch fabrics. Each of the switch fabrics has a switch core and a switch core access layer (SCAL). Each SCAL includes a receive element connected to an input port of the switch core and a transmit element connected to an output port of the switch core. The switch also includes a set of receive port adapters and a set of transmit port adapters. The receive port adapters are connected to both SCAL receive elements while the transmit port adapters are connected to both SCAL transmit adapters. Switch control logic assigns each port adapter to one of the switch fabrics during normal switch operation but re-assigns it to the other of the switch fabrics when the first switch fabric is taken out of service for planned maintenance or due to a component or system failure.